The XEP12K Embedded Processor / Camera Control System was designed and built by Xecon Associates to function as an Astronomical CCD Imager to be used in conjuction with the 24" Newtonian Reflecting Telescope located at the Hobbs Observatory (750) in Fall Creek, WI.
This camera system employs a 1024 x 1024 pixel CCD imaging chip (model numbers TK1024 or SI-003) fabricated by Scientific Imaging Technology Inc (SITE) of Beaverton, Oregon. This chip is fabricated using a thinned back illuminated process that greatly improves the dynamic spectral range and quantum efficiency of the device. The 24 micron square pixel size mechanized in this chip ideally match the focal parameters of the Hobbs 24" telescope. In telescope terms each indivdual pixel represents a sky area of 1.6241 x 1.6241 arc seconds. Accordingly, the full frame aperature of this camera system covers a viewed area approximately 0.46 degree square. The XEP12K design permits the pixels to be read out in either a left-to-right and top-to-bottom order, or in a right-to-left and bottom-to-top order depending upon the position of the telescope. This electronically selectable readout direction control permits straightforward Drift Scan operation without any physical alteration or adjustment of the camera proper when moving to different parts of the sky. [It should be noted that when TDI/Drift Scan imaging is requested, the STARTRAC telescope control program automatically rotates the Camera head so that the celestial RA axis is aligned with the parallel shift axis of the CCD.] Other features inherant in the chip/system design include: the selection or de-selection of on-chip (2x2) pixel binning, and readout operation in either the Normal mode or with the Multi-Pinned Phase(MPP) technology option.
The basic camera system design also has numerous other features including electronically initiated: shutter type selection (photometric and/or standard shutter) with timing control, a special focus read-out mode, line, partial frame or full frame image transfer, with similar operations for chip flush, automatic or microprocessor CCD chip temperature set control, and precision TDI/Drift Scan timing control. Operations are virtually transparent to the end user and are carried out by the XEP12K microprocessor via simple command. They include: expose (normal), expose (external trigger), take dark frame, take bias frame, expose focus, expose TDI, as well as the performance of system self-tests and status reporting.
The XEP12K Camera System contains essentially five component sections, namely: The physical Camera Head Enclosure (including aformentioned CCD chip), the XEP12K Camera Control Electronics, the Camera Power Supply Unit, the Camera to Computer Communications Cable, and the Computer Interface Assembly.
The physical Camera Head Assembly was designed and fabricated by Term Engineering, Skillman, New Jersey. The CCD chip was designed and fabricated by SITE, Inc. Beaverton, Oregon. The Camera Head Assembly is designed to accept and physically interface the CCD chip with a three stage thermoelectric cooler (TEC). The entire assembly is designed to operate in an evacuated condition so as to keep CCD chip at very low temperatures. A heat exchanger at the rear of the assembly removes heat pulled from the unit and CCD by the TEC. Light from the telescope enters the enclosure through a anti-reflective coated optical window at the front of the device. An electrical dew heater is provided at the junction of the optical window and the external world. A mechanical adaptor attached to the front of the head assembly interfaces directly with the telescope focusing unit. All electrical signals from the chip, TEC, and internal temperature sensor are conducted by a wiring harness to a 37 pin 'D' type connector located at the rear of the unit. This device also contains mounting provisions for a Melles-Griot model 04UTS204 electrically controlled shutter unit.
In addition to the above device, the Xecon/Hobbs Camera System contains an OPTEK MAXFILT 3-position filter slider assembly that may be operated in the system as a "photometric" type shutter. To use this device for this class of operation a MAXFILT slider with positions #1 and #3 opaque and position #2 open must be installed in the unit. Control electronics in the XEP12K system automatically keeps track of the slider position and controls the unit thereby mechanizing "photometric" shutter action. Alternately, the MAXFILT may be operated in the standard "filter" mode with the M-G device acting as the primary system shutter.
The XEP12K Camera Control Electronics consists of three small circuit boards and a power supply unit. There is also a small circuit board inside of the camera head assembly that assists in wiring the CCD to the 'D' connector and contains transistor impedance buffers for the CCD output amplifiers. The three boards in the control electronics assembly service the following functions: Analog Signal Processor, CCD Timing Generator, and the Control Processor. They are placed in a small enclosure that rides with the telescope and connects to the Camera Head Assembly via an 18" interconnect cable. The power supply sits on a bench directly below the telescope and connects to the control electronics assembly via an additional cable.
The Analog Signal Processor (ASP) board accepts low level pixel signals from the camera head as well as outputs from internal & external temperature sensors. As currently designed the ASP can accept pixel output signals from up to two CCD output amplifiers. These low level pixel inputs are first amplified by a low noise input pre-amplifier. The output of this amplifier is sent to a Correlated Double Sampler (CDS) the output of which is sent to a 16-bit A/D converter. Gain adjustments are provided by these circuits to correctly load the A/D converter. Design of the front end circuitry has been critically optimized for low noise performance. It is very similar to the front end design of the CCD interface to the Sloan Digital Sky Survey Cameras. [A description of those circuits may be found in an article written by Jim Gunn, et.al. (Princeton Univ.) published in The Astronomical Journal, Volume 116, No.8, 1998]. This front end design has been optimized to achieve very low noise levels as required when observing low intensity astronomical objects.
An alternate CDS-A/D Converter mechanization has also been completed that permits sampling and readout of the CCD pixels at a rate of 200K samples/sec. Current plans would only use this configuration when viewing higher intensity astronomical objects.
The ASP board contains potentiometers to adjust a number of voltages sent to the CCD chip, as well as video image gain and offsets for each of the two input channels. Additionally the board includes circuits for the system temperature sensors, calibration and readout.
The CCD Timing Generator board contains circuits used to generate switching voltages needed by the CCD chip to move charge packets across the device in the horizontal (line) and parallel (column) directions. Several other signals required by the CCD device are also generated to provide for resets, transfer gates, and summing wells. Line (horizontal) transfer and parallel (column) transfer timing signals are generated by two different Johnson counters and their associated decoders. Multiplexors following the decoders permit the charge buckets to be shifted in one of two different directions so as to simplify chip readout for Drift Scan imaging (described previously). Currently a majority of the timing logic for the CCD is implemented using a small Xilinx 9536 CPLD chip to reduce the board size. Operational amplifiers and associated potentiometers permit the various voltages needed by the CCD to be adjusted as required. MOS switches controlled by the timing circuits provide the switched voltages that are output to the CCD. Master control signals that enable CCD line or column charge movement are supplied from the Control Microprocessor unit.
The Control Processor board is constructed around an Atmel AT89C52 microprocessor chip. The architecture and instruction set of this device is essentially identical to the widely used 8052 family of embedded controllers. An added positive feature provided by the AT89C52 is 8K Words of flash memory for program code. This device can be purchased in either a 40 pin DIP package or a 44 pin PLCC. The prototype XEP12K card employed a DIP version of the microprocessor, but was later converted into the PLCC version of the device. The AT89C52 providesthe following standard features: 8K bytes of Flash, 256 bytes of RAM, 32 I/0 lines, three 16-bit counter-timers, a six vector two-level interrupt system, a full duplex serial communications port and an on-chip oscillator and clock circuitry. An external 11.0592 MHz crystal provides the time base source for both the microprocessor and the system. Additional CPLD and MSI/SSI circuits provide the I/O directors for signals to and from the microprocessor device.
The Control Microprocessor board additionaly contains a serial-to-serial translator for the image (digitized pixel) data coming from the A/D converter. The incoming 16-bit A/D word is tagged and modified into a 20-bit video word that will be serially sent to the controlling PC over a CAT5 cable. The video data is tagged to indicate whether the specific pixel is an overscan-underscan or actual image pixel, a chip temperature reading, or a system test word. This arrangement permits the interface board at receiving PC to seperate out different pieces of data and place them into appropriate memory locations. Most of these logic processes are implemented with a Xilinx 95108 CPLD chip. Both a high speed video clock and data component are sent over seperate twisted pairs of the CAT5 cable at a rate of approximately 5.6 MHz. This data rate was designed to keep up with the highest A/D CCD chip pixel conversion rate currently designed for of 200K samples/sec.
A full 1024 x 1024 pixel image can be completely read out from the camera and transferred to the controlling PC in less than 12 seconds when using the high precision CDS-A/D system operating at 100K conversions/sec. An image that has been binned 2x2 on the CCD chip reads out in less than 3 seconds using this mechanization. When the alternate CDS-A/D converter system operating at a rate of 200K pixel samples/sec is used, the 16-bit 1024x1024 image may be fully read out to the PC in less than 6 seconds.
The communication link between Camera and PC as currently configured could operate effectively at conversion rates greatly in excess of any conceivable for a CCD imaging device of this nature.
It should be noted that the ONLY CONNECTION between the XEP12K Camera Control electronics and the Controlling IBM PC is a SINGLE CAT5 cable. In additon to the video data described above, the other two pairs within this cable are used to transmit commands from the controlling PC to the camera and receive return system status replies. These later two signal pairs interface directly with the AT89C52 microprocessor serial communications port after level translation. This CAT5 communication link is designed to easily work up to distances of 500 feet or more.
The control "intelligence" of this whole package resides in the program code of the AT89C52 microprocessor. Since it is burned into the flash memory it is often referred to as "firmware". The entire program for this device is built around a Xecon Real Time Operating System (RTOS). For optimum efficiency and precision timing control , the AT89C52 is programmed in machine (assembly) language. Two of the six available machine interrupts are used in this design. Counter-timer #2 is used to generate an RTOS interrupt once every 250 microseconds. Counter-timer #3 is used to generate a precision interrupt for Drift Scan timing. Counter-timer #1 is used to generate timing for the serial communications port, but no interrupt is used (the RTOS handles this function). A brief discussion follows.
The RTOS for this system is built around a 250 microsecond control loop. Once every 250 microseconds the AT89C52 is forced to re-enter the real-time in-line control code. All critical system timing (with the exception of Drift Scan timing) are performed by this code. This includes the monitoring of the serial I/O communications link, the timing of all camera control functions, and the incorporation of the system 0.1 and 1 second tick counters. As currently designed the real time in-line control code contains about 95 machine instructions, executes in about 110 microseconds and consumes about 22% of the total timing budget. Timed Delay Integration (TDI) Drift Scan timing boundaries are accurate to about 1.085 microseconds, or 12X the crystal period (12/11.0592 E+6), and only require about 15 special machine instructions.
Most of the detailed, non-time critical, functions for this system are handled by the system task and sub-task schedulers. System code is basically constructed around a round-robin task scheduler. Each scheduled task is coded to execute in as small a time as possible. Control is then simply passed on to the next scheduled task. This process repeats and loops continously giving all tasks equal and shared access to the micorprocessor until interrupted by a major system timing event. After the timing event is complete, control is returned back to the task scheduler. The unique nature of this system requires that the XEP12K code also contains a sub-task handler. This simply means that a given task may be broken down into a series of sub-tasks that process in time sequential order. For example consider the basic "expose" task. To accomplish this function the microprocessor performs the following operations in time sequential order: (1) Flush (clear) the CCD chip, (2) Open the sepecified shutter, (3) Time-out the shutter open period, (4) Close the specified shutter, (5) Initiate the proper signals to read out individual CCD lines, parallel shift the CCD as required, and return the image to the main PC. Upon completion of the final sub-task, the overall task is suspended and this task slot enters an idle state.
As discussed previously, commands are sent to the XEP12K Camera System microcontroller from the main PC over the CAT5 cable interface. This particular system design incorporates about 30 generic command types to achieve the requisite flexibilty for system operation, examination and test.
The XEP12K Camera System is designed to accomodate a simple interface connection with the controlling PC. The current design implementation for the Hobbs Observatory uses a special ISA plug-in board that can operate with any AT or greater IBM style PC.
The PC interface assembly performs two essential functions: (1) serial to parallel conversion of the high speed video data with provisions to insert these words into the PC's memory as they arrive, and (2) signal interfacing to a standard serial I/O channel that is capable of operating at a rate of at least 9600 baud with appropriate level conversion. This simple structure permits the Camera to interface with virtually any standard PC bus, namely: ISA, PCI, SCSI, EPP/ECP, or 3GIO with an appropriately designed converter assembly and associated PC control software. [It should be pointed out that the PC software for certain bus system types may be difficult to implement from the standoint of trying to "keep-up" with the incoming video (pixel) data rate. Our ISA bus approach was specifically designed to preclude this problem. The ISA bus is capable of transferring data to/from the computers memory at a clock rate of 8 Mhz [8 Mwords (16 Mbytes) per second]. A PCI bus system is capable of transferring data to/from memory at a rate of up to 132 MBytes per second when using a 33Mhz clock. The 3GIO interface is still in the definition phase.]
At the Hobbs Observatory the most flexible and simply programmed PC interface uses an ISA bus approach. For the video (image) channel the card detects and converts an incoming camera word, determines its type (image, temp, or extra-scan) and automatically inserts the respective word into the proper PC memory location. An on-board DMA controller handles a majority of the work. Program intervention is required only between DMA blocks on a non-time critical basis. This design also permits for fast memory-to-memory transfers that allow images to be rapidly moved between RAM, video display or bulk storage. The serial I/O interface is mechanized on-board using a National PC16550 communications chip with external level shifters. This precludes the need to use one of the existing PC serial I/O ports. PC software to control and operate the camera consists of programming and managing the DMA controllers (for image & misc. memory locations), the generation of basic camera commands, and the monitoring of system status. It should be emphasized that because of the way that this system has been designed, the PC generated commands are essentially non-time critical. Functions that are time critical execute based upon timing developed by the Camera-microcontroller clock system. Data reduction and analysis for images taken with the XEP12K Camera System are made with the Astro Imaging Analyst program.